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18-bit, 1.5 lsb inl, 250 ksps pulsar ? differential adc in msop/qfn AD7691 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 18-bit resolution with no missing codes throughput: 250 ksps inl: 0.75 lsb typ, 1.5 lsb max (6 ppm of fsr) dynamic range: 102 db typ @ 250 ksps oversampled dynamic range: 125 db @1 ksps noise-free code resolution: 20 bits @ 1 ksps effective resolution: 22.7 bits @ 1 ksps sinad: 101.5 db typ @ 1 khz thd: ?125 db typ @ 1 khz true differential analog input range: v ref 0 v to v ref with v ref up to vdd on both inputs no pipeline delay single-supply 2.3 v to 5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface serial interface spi?/qspi?/microwire?/dsp compatible daisy-chain multiple adcs and busy indicator power dissipation 5 mw @ 5 v/250 ksps 50 w @ 5 v/1 ksps standby current: 1 na 10-lead package: msop (msop-8 size) and 3 mm 3 mm qfn 1 (lfcsp) (sot-23 size) pin-for-pin compatible with the18-bit ad7690 and 16-bit ad7693, ad7688, and ad7687 applications battery-powered equipment data acquisitions seismic data acquisition systems dvms instrumentation medical instruments 1.5 ?1.5 0 262144 code inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 65536 131072 196608 positive inl = 0.43lsb negative inl = ?0.62lsb 06146-025 figure 1. integral nonlinearity vs. code, 5 v application diagram AD7691 ref gnd vdd in+ in? vio sdi sck sdo cnv +1.8v to vdd 3- or 4-wire interface (spi, daisy chain, cs) +2.3v to vdd 10v, 5v, ... +2.3v to +5v ada4941 0 6146-001 figure 2. table 1. msop, qfn 1 (lfcsp)/sot-23 14-/16-/18-bit pulsar adc type 100 ksps 250 ksps 400 ksps to 500 ksps adc driver 18-bit AD7691 ad7690 ada4941-1 ada4841-x 16-bit true differential ad7684 ad7687 ad7688 ad7693 ada4941-1 ada4841-x 16-bit pseudo ad7683 ad7685 ad7686 ada4841-x differential/ unipolar ad7680 ad7694 14-bit ad7940 ad7942 ad7946 ada4841-x 1 qfn package in developm ent. contact sales for samples and availability. general description the AD7691 is an 18-bit, charge redistribution, successive approximation, analog-to-digital converter (adc) that operates from a single power supply, vdd, between 2.3 v and 5 v. it contains a low power, high speed, 18-bit sampling adc with no missing codes, an internal conversion clock, and a versatile serial interface port. on the cnv rising edge, it samples the voltage difference between the in+ and in? pins. the voltages on these pins usually swing in opposite phase between 0 v and ref. the reference voltage, ref, is applied externally and can be set up to the supply voltage. its power scales linearly with throughput. the spi-compatible serial interface also features the ability, using the sdi input, to daisy-chain several adcs on a single 3-wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate vio supply. the AD7691 is housed in a 10-lead msop or a 10-lead qfn 1 (lfcsp) with operation specified from ?40c to +85c. 1 qfn package in developm ent. contact sales for samples and availability.
AD7691 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 application diagram........................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configurations and function descriptions ........................... 8 terminology ...................................................................................... 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 13 circuit information.................................................................... 13 converter operation.................................................................. 13 typical connection diagram ................................................... 14 analog inputs ............................................................................. 15 driver amplifier choice ........................................................... 15 single-to-differential driver .................................................... 16 voltage reference input ............................................................ 16 power supply............................................................................... 16 supplying the adc from the reference.................................. 17 digital interface.......................................................................... 17 application hints ........................................................................... 24 layout .......................................................................................... 24 evaluating the AD7691s performance.................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 7/06revision 0: initial version
AD7691 rev. 0 | page 3 of 28 specifications vdd = 2.3 v to 5.25 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 2. parameter conditions/comments min typ max unit resolution 18 bits analog input voltage range, v in in+ ? (in?) ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common-mode input range in+, in? 0 v ref /2 v ref /2 + 0.1 v analog input cmrr f in = 250 khz 65 db leakage current at 25c acquisition phase 1 na input impedance 1 throughput conversion rate vdd = 4.5 v to 5.25 v 0 250 ksps vdd = 2.3 v to 4.5 v 0 180 ksps transient response full-scale step 1.8 s accuracy no missing codes 18 bits integral linearity error ?1.5 0.75 +1.5 lsb differential linearity error ?1 0.5 +1.25 lsb 2 transition noise ref = vdd = 5 v 0.75 lsb gain error 3 vdd = 4.5 v to 5.25 v ?45 2 +45 lsb vdd = 2.3 v to 4.5 v ?80 2 +80 lsb gain error temperature drift 0.5 ppm/c zero error 3 vdd = 4.5 v to 5.25 v ?0.8 0.1 +0.8 mv vdd = 2.3 v to 4.5 v ?3.5 0.7 +3.5 mv zero temperature drift 1 ppm/c power supply sensitivity vdd = 5 v 5% 0.25 lsb ac accuracy dynamic range v ref = 5 v 101 102 db 4 oversampled dynamic range 5 f in = 1 ksps 125 db signal-to-noise f in = 1 khz, v ref = 5 v 100 101.5 db f in = 1 khz, v ref = 2.5 v 95 96.5 db spurious-free dynamic range f in = 1 khz, v ref = 5 v ?125 db total harmonic distortion f in = 1 khz, v ref = 5 v ?118 db signal-to-(noise + distortion) f in = 1 khz, v ref = 5 v 100 101.5 db f in = 1 khz, v ref = 2.5 v 95 96.5 db intermodulation distortion 6 115 db 1 see the analog inputs section. 2 lsb means least significant bit. with the 5 v input range, one lsb is 38.15 v. 3 see the terminology section. these specif ications include full temperature range variation but not the error contribution from the external reference. 4 all specifications in db are referred to a full-scale input fsr. tested with an input signal at 0.5 db below full scale, unles s otherwise specified. 5 dynamic range obtained by oversampli ng the adc running at a throughput f s of 250 ksps, followed by postdigital fi ltering with an outp ut word rate f o . 6 f in1 = 21.4 khz and f in2 = 18.9 khz, with each tone at ?7 db below full scale.
AD7691 rev. 0 | page 4 of 28 vdd = 2.3 v to 5.25 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 3. parameter conditions/comments min typ max unit reference voltage range 0.5 vdd + 0.3 v load current 250 ksps, ref = 5 v 60 a sampling dynamics ?3 db input bandwidth 2 mhz aperture delay vdd = 5 v 2.5 ns digital inputs logic levels v il ?0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 18-bit, twos complement. pipeline delay 1 v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 2.3 5.25 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 2 , 3 vdd and vio = 5 v, 25c 1 50 na power dissipation 100 sps throughput 5 w 100 ksps throughput 4 mw 250 ksps throughput 5 mw energy per conversion 50 nj/sample temperature range 4 specified performance t min to t max ?40 +85 c 1 conversion results are available imme diately after completed conversion. 2 with all digital inputs forced to vio or gnd as required. 3 during acquisition phase. 4 contact an analog devices, inc., sales representative for extended temperature range.
AD7691 rev. 0 | page 5 of 28 timing specifications vdd = 4.5 v to 5.25 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 4. 1 parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 2.2 s acquisition time t acq 1.8 s time between conversions t cyc 4 s cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck 15 ns sck period (chain mode) t sck vio above 4.5 v 17 ns vio above 3 v 18 ns vio above 2.7 v 19 ns vio above 2.3 v 20 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 4 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d17 msb valid ( cs mode) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 15 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 10 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 3 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns 1 see figure 3 and figure 4 for load conditions.
AD7691 rev. 0 | page 6 of 28 vdd = 2.3 v to 4.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 5. 1 parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 3.7 s acquisition time t acq 1.8 ns time between conversions t cyc 5.5 s cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck 25 ns sck period (chain mode) t sck vio above 3 v 29 ns vio above 2.7 v 35 ns vio above 2.3 v 40 ns sck low time t sckl 12 ns sck high time t sckh 12 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo vio above 3 v 24 ns vio above 2.7 v 30 ns vio above 2.3 v 35 ns cnv or sdi low to sdo d17 msb valid ( cs mode) t en vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 30 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 8 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 8 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 10 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 36 1 see figure 3 and figure 4 for load conditions.
AD7691 rev. 0 | page 7 of 28 absolute maximum ratings table 6. parameter rating analog inputs in+, 1 in? 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance (10-lead msop) 200c/w jc thermal impedance (10-lead msop) 44c/w lead temperature range jedec j-std-20 1 see the analog inputs section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 500a i ol 500a i oh 1.4v to sdo c l 50pf 05792-002 figure 3. load circuit fo r digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 1 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. 05792-003 figure 4. voltage levels for timing
AD7691 rev. 0 | page 8 of 28 pin configurations and function descriptions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 AD7691 top view (not to scale) 06146-004 figure 5. 10-lead msop pin configuration 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio notes 1. qfn package in development. contact sales for samples and availability. 9sdi 8sck 7sdo 6cnv top view (not to scale) AD7691 0 6146-005 figure 6. 10-lead qfn (lfcsp) pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd. it is referred to the gnd pin. this pin should be decoupled closely to the pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the part, either chain or cs mode. in cs mode, it enables the sdo pin when low. in chain mode, the data should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 18 sck cycles. cs mode is selected if sdi is high during the cn v rising edge. in this mode, either sdi or cnv can enable the serial output signals when low, an d if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 1 ai = analog input, di = digital input, do = digital output, and p = power.
AD7691 rev. 0 | page 9 of 28 terminology least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that can be represented by a converter. for an analog-to-digital con- verter with n bits of resolution, the lsb expressed in volts is n inpp v lsb 2 )v( = integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 26 ). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 . . . 00 to 100 . . . 01) should occur at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) should occur for an analog voltage 1? lsb below the nominal full scale (+4.999943 v for the 5 v range.) the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula: enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise-free code resolution it is the number of bits beyond which it is impossible to resolve individual codes distinctly. it is calculated as noise-free code resolution = log 2 (2 n / peak-to-peak noise ) and is expressed in bits. effective resolution it is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse transient response is the time required for the adc to acquire its input accurately after a full-scale step function is applied.
AD7691 rev. 0 | page 10 of 28 typical performance characteristics 1.5 ?1.5 0 262144 code inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 65536 131072 196608 positive inl = 0.39lsb negative inl = ?0.73lsb 06146-026 figure 7. integral nonlinearity vs. code 2.5 v 80k 0 25 code in hex counts 70k 60k 50k 40k 30k 20k 10k 26 27 28 29 2a 2b 2c 2d 2e 2f 0 0 26 2062 14 0 0 2904 69769 28527 27770 vdd = ref = 5v = 0.76lsb 06146-027 figure 8. histogram of a dc input at the code center, 5 v 0 ?180 0 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 20 40 60 80 100 120 32768 point fft vdd = ref = 5v f s = 250ksps f in = 2khz snr = 101.4db thd = ?120.1db 2nd harmonic = ?140.7db 3rd harmonic = ?120.3db 06146-028 figure 9. 2 khz fft plot, 5 v 1.0 ?1.0 0 262144 code dnl (lsb) 0.5 0 ?0.5 65536 131072 196608 positive dnl = 0.37lsb negative dnl = ?0.33lsb 06146-029 figure 10. differential nonlinearity vs. code, 5 v 45k 0 code in hex counts 2423 25 26 28 29 2b2a 2c 2d 2f2e 30 31 01229 501 910 78 9 0 17460 28179 vdd = ref = 2.5v = 1.42lsb 14362 24411 27 2997 38068 06146-030 40k 35k 30k 25k 20k 15k 10k 5k 4055 figure 11. histogram of a dc input at the code center, 2.5 v 0 ?180 0 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 2010 30 40 50 60 70 80 90 32768 point fft vdd = ref = 2.5v f s = 180ksps f in = 2khz snr = 96.4db thd = ?120.3db 2nd harmonic = ?132.5db 3rd harmonic = ?121.2db 06146-031 figure 12. 2 khz fft plot, 2.5 v
AD7691 rev. 0 | page 11 of 28 104 86 92 90 88 2.3 5.3 4.7 5.0 reference voltage (v) snr, sinad (db) 102 100 98 96 94 14 enob (bits) 18 17 16 15 2.6 2.9 3.2 3.5 3.8 4.1 4.4 enob sinad 06146-032 snr figure 13. snr, sinad, and enob vs. reference voltage 105 100 95 90 85 80 ?55 125 temperature (c) snr (db) ?35 ?15 5 25 45 65 85 105 06146-033 v ref = 5v v ref = 2.5v figure 14. snr vs. temperature 105 70 0 125 frequency (khz) sinad (db) 100 95 90 85 80 75 25 50 75 100 v ref = 5v, ?1db v ref = 2.5v, ?10db v ref = 2.5v, ?1db v ref = 5v, ?10db 06146-037 figure 15. sinad vs. frequency ? 105 ?135 ?125 ?130 2.3 5.3 reference voltage (v) thd, sfdr (db) 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 ?110 ?115 ?120 06146-038 thd sfdr figure 16. thd, sfdr vs. reference voltage ? 90 ?130 ?55 125 temperature (c) thd (db) ?35 ?15 5 25 45 65 85 105 v ref = 5v v ref = 2.5v ?100 ?110 ?120 06146-039 figure 17. thd vs. temperature ? 60 ?130 0 125 frequency (khz) thd (db) ?70 ?80 ?90 ?100 ?110 ?120 25 50 75 100 v ref = 5v, ?1db v ref = 2.5v, ?10db v ref = 2.5v, ?1db v ref = 5v, ?10db 06146-040 figure 18. thd vs. frequency
AD7691 rev. 0 | page 12 of 28 105 81 ?10 0 input level (db) snr (db) ?130 thd (db) ? 90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 06146-041 102 99 96 93 90 87 84 ?8 ?6 ?4 ?2 snr 2.5v snr 5v thd 2.5v thd 5v figure 19. snr, thd vs. input level temperature (c) operating current (a) 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 vio vdd = 2.5v vdd = 5v 0 6146-042 f s =100ksps figure 20. operating current vs. temperature supply (v) operating current (a) 1000 750 500 250 0 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 vio vdd 0 6146-043 f s =100ksps figure 21. operating current vs. supply 6 ?6 temperature (c) offset, gain error (lsb) ?55 125 4 2 0 ?2 ?4 ?35 ?15 5 25 45 65 85 105 gain error offset error 06146-044 figure 22. offset and gain error vs. temperature temperature (c) power-down current (na) 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 vdd + vio 0 6146-047 figure 23. power-down current vs. temperature sdo capacitive load (pf) 120 0 20406080100 t dsdo delay (ns) 25 20 15 10 5 0 vdd = 5v, 85c vdd = 5v, 25c 0 6146-034 figure 24. t dsdo delay vs. capacitance load and supply
AD7691 rev. 0 | page 13 of 28 theory of operation sw+ msb 65,536c in + lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 131,072c sw? msb 65,536c lsb 4c 2c c c 131,072c 0 5792-006 figure 25. adc simplified schematic circuit information the AD7691 is a fast, low power, single-supply, precise, 18-bit adc using a successive approximation architecture. the AD7691 is capable of converting 250,000 samples per second (250 ksps) and powers down between conversions. when operating at 1 ksps, for example, it consumes 50 w typically, which is ideal for battery-powered applications. the AD7691 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the AD7691 is specified from 2.3 v to 5.25 v and can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 10-lead msop or a tiny 10-lead qfn 1 (lfcsp) that combines space savings and allows flexible configurations. it is pin-for-pin compatible with the 18-bit ad7690 as well as the 16-bit ad7687 and ad7688. converter operation the AD7691 is a successive approximation adc based on a charge redistribution dac. figure 25 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary-weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs in+ and in? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary-weighted voltage steps (v ref /2, v ref /4 ... v ref /262,144). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the AD7691 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process. 1 qfn package in developm ent. contact sales for samples and availability.
AD7691 rev. 0 | page 14 of 28 transfer functions the ideal transfer characteristic for the AD7691 is shown in figure 26 and table 8 . 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 05792-007 figure 26. adc ideal transfer function table 8. output codes and ideal input voltages description analog input v ref 5 v digital output code (he) fsr ? 1 lsb +4.999962 v 0x2ffff 1 midscale + 1 lsb +38.15 v 0x00001 midscale 0 v 0x00000 midscale ? 1 lsb ?38.15 v 0x3ffff ?fsr + 1 lsb ?4.999962 v 0x20001 ?fsr ?5 v 0x20000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). typical connection diagram figure 27 shows an example of the recommended connection diagram for the AD7691 when multiple supplies are available. AD7691 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire interface 5 100nf 100nf 5v 10f 2 v+ v+ v? 1.8v to vdd ref 1 0 to v ref 15? 2.7nf 4 v+ v? v ref to 0 15? 2.7nf ada4841-2 3 ada4841-2 3 4 1 see reference section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). 3 see table 9 for additional recommended amplifiers. 4 optional filter. see analog input section. 5 see the digital interface section for most convenient interface mode. 06146-008 figure 27. typical application diagram with multiple supplies
AD7691 rev. 0 | page 15 of 28 analog inputs figure 28 shows an equivalent circuit of the input structure of the AD7691. the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 v because this causes the diodes to become forward biased and start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions could eventually occur if the input buffers (u1s) supplies are different than vdd. in such a casefor example, an input buffer with a short circuitthe current limitation can be used to protect the part. c in r in d1 d2 c pin in+ or in? gnd v dd 05792-009 figure 28. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. 90 40 1 10000 frequency (khz) cmrr (db) 10 100 1000 85 80 75 70 65 60 55 50 45 v ref = vdd = 5v 06146-036 figure 29. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ and in?) can be modeled as a parallel combination of the capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 3 k and is a lumped component made up of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the AD7691 can be driven directly. large source impedances significantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier choice although the AD7691 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the AD7691. the noise coming from the driver is filtered by the AD7691 analog input circuits 1-pole, low-pass filter made by r in and c in or by the external filter, if one is used. the snr degradation due to the amplifier is as follows: ? ? ? ? ? ? ? ? ? ? ? ? + + = ? ? + ? 2 db3 2 db3 2 )( 2 )( 2 log20 n n nadc nadc loss nefnef v v snr where: v nadc is the noise of the adc, in v, given by the following: 20 10 22 snr inpp nadc v v = f ?3 db is the input bandwidth , in mhz, of the AD7691 (2 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n+ and e n? are the equivalent input noise voltage densities of the op amps connected to in+ and in?, in nv/hz. this approximation can be used when the resistances around the amplifier are small. if larger resistances are used, their noise contributions should also be root-sum- squared. ? for ac applications, the driver should have a thd performance commensurate with the AD7691. ? for multichannel multiplexed applications, the driver amplifier and the AD7691 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.0004%, 4 ppm). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at an 18-bit level and should be verified prior to driver selection.
AD7691 rev. 0 | page 16 of 28 table 9. recommended driver amplifiers amplifier typical application ada4941-1 very low noise, low power single-ended-to- differential driver ada4841-x very low noise, small, and low power ad8655 5 v single supply, low noise ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605, ad8615 5 v single supply, low power single-to-differ ential driver for applications using a single-ended analog signal, either bipolar or unipolar, the ada4941-1 single-ended-to-differential driver allows for a differential input into the part. the schematic is shown in figure 30 . r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2, and c f are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. for example, for the 10 v range with a 4 k impedance, r2 = 1 k and r1 = 4 k. r3 and r4 set the common mode on the in? input, and r5 and r6 set the common mode on the in+ input of the adc. the common mode should be set close to v ref /2; however, if single supply is desired, it can be set slightly above v ref /2 to provide some headroom for the ada4941-1 output stage. for example, for the 10 v range with a single supply, r3 = 8.45 k, r4 = 11.8 k, r5 = 10.5 k, and r6 = 9.76 k. AD7691 ref gnd vdd in+ 2.7nf 100nf 2.7nf in? +5v ref 10v, 5v, ... +5.2v +5.2v 15 ? 10f 15 ? r2 c f ada4941 r1 r3 100nf r5 r4 r6 06146-010 figure 30. single-ended-to- differential driver circuit voltage reference input the AD7691 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source, for example, a reference buffer using the ad8031 or the ad8605, a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, smaller reference decoupling capacitor valuesdown to 2.2 fcan be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the AD7691 uses two power supply pins: a core supply, vdd, and a digital input/output interface supply, vio. vio allows direct interface with any logic between 1.8 v and vdd. to reduce the supplies needed, the vio and vdd pins can be tied together. the AD7691 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 31 . 95 65 1 10000 frequency (khz) psrr (db) 90 85 80 75 70 10 100 1000 06146-035 figure 31. psrr vs. frequency
AD7691 rev. 0 | page 17 of 28 the AD7691 powers down automatically at the end of each conversion phase, and therefore the power scales linearly with the sampling rate. this makes the part ideal for low sampling rate (as low as a few hertz) and low battery-powered applications. 1000 10 0.1 0.001 10 1m sampling rate (sps) operating current (a) 100 1k 100k 10k vdd = 5v vio 06146-045 figure 32. operating current vs. sample rate supplying the adc from the reference for simplified applications, the AD7691, with its low operating current, can be supplied directly using the reference circuit shown in figure 33 . the reference line can be driven by ? the system power supply directly. ? a reference voltage with enough current output capability, such as the adr43x. ? a reference buffer, such as the ad8031, which can also filter the system power supply, as shown in figure 33 . ad8031 AD7691 vio ref vdd 10f 1f 10? 10k ? 5v 5v 5v 1f 1 1 optional reference buffer and filter. 06146-046 figure 33. example of an application circuit digital interface though the AD7691 has a reduced number of pins, it offers flexibility in its serial interface modes. when in cs mode, the AD7691 is compatible with spi, qspi, digital hosts, and dsps, for example, black fin ? adsp-bf53x or adsp-219x. in this mode, the AD7691 can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections and is useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. when in chain mode, the AD7691 provides a daisy-chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high, and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is selected. in either mode, the AD7691 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. the busy indicator feature is enabled ? in the cs mode if cnv or sdi is low when the adc conversion ends (see figure 37 and figure 41 ). ? in the chain mode if sck is high during the cnv rising edge (see figure 45 ).
AD7691 rev. 0 | page 18 of 28 3-wire cs mode without busy indicator this mode is usually used when a single AD7691 is connected to an spi-compatible digital host. the connection diagram is shown in figure 34 , and the corresponding timing is given in figure 35 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this could be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers, but cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the AD7691 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge can allow a faster reading rate, provided it has an acceptable hold time. after the 18 th sck falling edge, or when cnv goes high, whichever is earlier, sdo returns to high impedance. cnv sck sdo sdi data in clk convert v io digital host AD7691 06146-011 figure 34. 3-wire cs mode without busy indicator connection diagram (sdi high) sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 16 17 18 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 05792-012 figure 35. 3-wire cs mode without busy indicator seri al interface timing (sdi high)
AD7691 rev. 0 | page 19 of 28 3-wire cs mode with busy indicator this mode is usually used when a single AD7691 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 36 , and the corresponding timing is given in figure 37 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by th e digital host. the AD7691 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge can allow a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge, or when cnv goes high, whichever is earlier, sdo returns to high impedance. if multiple AD7691s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. data in irq clk convert vio digital host 47k? cnv sck sdo sdi v io AD7691 06146-013 figure 36. 3-wire cs mode with busy indicator connection diagram (sdi high) sdo d17 d16 d1 d0 t dis sck 123 171819 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq 05792-014 figure 37. 3-wire cs mode with busy indi cator serial interface timing (sdi high)
AD7691 rev. 0 | page 20 of 28 4-wire cs mode without busy indicator this mode is usually used when multiple AD7691s are connected to an spi-compatible digital host. a connection diagram example using two AD7691s is shown in figure 38 , and the corresponding timing is given in figure 39 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the AD7691 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the 18 th sck falling edge, or when sdi goes high, whichever is earlier, sdo returns to high impedance and another AD7691 can be read. data in clk cs1 convert cs2 digital host cnv sck sdo sdi cnv sck sdo sdi AD7691 AD7691 06146-015 figure 38. 4-wire cs mode without busy indicator connection diagram sdo d17 d16 d15 d1 d0 t dis sck 123 343536 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition s di (cs1) cnv t ssdicnv t hsdicnv d1 16 17 t sck t sckl t sckh d0 d17 d16 19 20 18 s di (cs2) 06146-016 figure 39. 4-wire cs mode without busy indicato r serial interface timing
AD7691 rev. 0 | page 21 of 28 4-wire cs mode with busy indicator this mode is usually used when a single AD7691 is connected to an spi-compatible digital host, which has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 40 , and the corresponding timing is given in figure 41 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the AD7691 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge can allow a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge, or sdi going high, whichever is earlier, sdo returns to high impedance. data in irq clk convert cs1 vio digital host 47k ? cnv sck sdo sdi AD7691 06146-017 figure 40. 4-wire cs mode with busy indicator connection diagram sdo d17 d16 d1 d0 t dis sck 1 2 3 171819 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 05792-018 figure 41. 4-wire cs mode with busy indicator serial interface timing
AD7691 rev. 0 | page 22 of 28 chain mode without busy indicator this mode can be used to daisy-chain multiple AD7691s on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two AD7691s is shown in figure 42 , and the corresponding timing is given in figure 43 . when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the AD7691 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge can allow a faster reading rate and consequently more AD7691s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate can be reduced due to the total readback time. clk convert data in digital host cnv sck sdo sdi cnv sck sdo sdi AD7691 b AD7691 a 06146-019 figure 42. chain mode without busy indicator connection diagram sdo a = sdi b d a 17 d a 16 d a 15 sck 123 343536 t ssdisck t hsdisc t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 16 17 t sck t sckl t sckh d a 0 19 20 18 sdi a = 0 sdo b d b 17 d b 16 d b 15 d a 1 d b 1d b 0d a 17 d a 16 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 05792-020 figure 43. chain mode without busy indicator serial interface timing
AD7691 rev. 0 | page 23 of 28 chain mode with busy indicator this mode can also be used to daisy-chain multiple AD7691s on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three AD7691s is shown in figure 44 , and the corresponding timing is given in figure 45 . when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the AD7691 adc labeled c in figure 44 ) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the AD7691 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more AD7691s in the chain, provided the digital host has an acceptable hold time. clk convert data in irq digital host cnv sck sdo sdi cnv sck sdo sdi cnv sck sdo sdi AD7691 b AD7691 c AD7691 a 0 6146-021 figure 44. chain mode with bu sy indicator connection diagram sdo a = sdi b d a 17 d a 16 d a 15 sck 123 39 53 54 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 417 t sck t sckh t sckl d a 0 19 38 18 sdo b = sdi c d b 17 d b 16 d b 15 d a 1 d b 1d b 0d a 17 d a 16 55 t ssdisck t hsdisc t hsdo t dsdo sdo c d c 17 d c 16 d c 15 d a 1d a 0 d c 1d c 0d a 16 21 35 36 20 37 d b 1d b 0d a 17 d b 17 d b 16 t dsdosdi t ssckcnv t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi 05792-022 figure 45. chain mode with busy indicator serial interface timing
AD7691 rev. 0 | page 24 of 28 application hints layout the printed circuit board that houses the AD7691 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the AD7691, with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because this couples noise onto the die unless a ground plane under the AD7691 is used as a shield. fast switching signals, such as cnv or clocks, should not run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it could be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the AD7691. the AD7691 voltage reference input, ref, has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. finally, the power supplies, vdd and vio, of the AD7691 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the AD7691 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 46 and figure 47 . evaluating the AD7691s performance other recommended layouts for the AD7691 are outlined in the documentation of the evaluation board for the AD7691 (eval-AD7691-cb). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3. 0 6146-023 figure 46. example layout of the AD7691 (top layer) 05792-024 figure 47. example layout of the AD7691 (bottom layer)
AD7691 rev. 0 | page 25 of 28 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 48.10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 3.00 bsc sq index are a top view 1.50 bcs sq exposed pad (bot tom view) 1.74 1.64 1.49 2.48 2.38 2.23 1 6 10 0.50 bsc 0.50 0.40 0.30 5 pin 1 indicator 0.80 0.75 0.70 0.05 max 0.02 nom seating plane 0.30 0.23 0.18 0.20 ref 0.80 max 0.55 typ side view paddle connected to gnd. this connection is not required to meet the electrical performances figure 49. 10-lead lead frame chip scale package [qfn (lfcsp_wd)] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters qfn package in development. contact sales for samples and availability. ordering guide model temperature range ordering quantity pa ckage description package option branding AD7691brmz 1 C40c to +85c tube, 50 10-lead msop rm-10 c4e AD7691brmz-rl7 1 C40c to +85c reel, 1,000 10-lead msop rm-10 c4e eval-AD7691cb 2 evaluation board eval-control brd2 3 controller board eval-control brd3 3 controller board 1 z = pb-free part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brdx for evaluation/demonstrat ion purposes. 3 these boards allow a pc to control and communicate with all analog devices evaluation boards ending in the cb designators.
AD7691 rev. 0 | page 26 of 28 notes
AD7691 rev. 0 | page 27 of 28 notes
AD7691 rev. 0 | page 28 of 28 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06146-0-7/06(0)

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